Programmable logic devices (PLDs) typically include a plurality of logic elements and associated interconnect resources that are programmed by a user to implement user-defined logic operations (e.g., an application specific circuit design). A PLD is typically programmed using programming software that is provided by the PLD's manufacturer, a personal computer or workstation capable of running the programming software, and a device programmer. In contrast, application specific integrated circuits (ASICs) have fixed-function logic circuits and fixed signal routing paths, and require a protracted layout process and an expensive fabrication process to implement a user's logic operation. Because PLDs can be utilized to implement logic operations in a relatively quick and inexpensive manner, PLDs are often preferred over ASICs for many applications.
FIG. 1(A) shows an example of a field programmable gate array (FPGA) 100, which is one type of PLD. Although greatly simplified, FPGA 100 is generally consistent with XC3000.TM. series FPGAs, which are produced by Xilinx, Inc. of San Jose, Calif.
FPGA 100 includes an array of configurable logic blocks (CLBs) 1,1 through 4,4 surrounded by input/output blocks (IOBs) IOB-1 through IOB-16, and programmable interconnect resources that include vertical interconnect segments 120 and horizontal interconnect segments 121 extending between the rows and columns of CLBs and IOBs. The CLBs, IOBs and programmable interconnect resources of FPGA 100 form a discrete circuit that resides on a silicon chip.
Each CLB includes configurable combinational circuitry and optional output registers that are programmed to implement logic in accordance with CLB configuration data stored in configuration memory cells (not shown) of FPGA 100. Data is transmitted into each CLB on input wires 110 and is transmitted from each CLB on output wires 115. The configurable combinational circuitry of each CLB implement a portion of a logic operation responsive to signals received on input wires 110 in accordance with the CLB configuration data stored in the configuration memory cells associated with that CLB. Similarly, the optional output registers of each CLB transmit signals from the CLB onto a selected output wire 115 in accordance with the stored CLB configuration data. Typically, all of the CLBs of an FPGA include identical configurable circuitry.
Each IOB includes configurable circuitry that is controlled by associated configuration memory cells, which are programmed to store IOB configuration data. In accordance with the IOB configuration data, each IOB selectively allows an associated pin (not shown) of FPGA 100 to be used either for receiving input signals from other devices, or for transmitting output signals to other devices. Similar to the CLBs, all of the IOBs of an FPGA typically include identical configurable circuitry.
The programmable interconnect resources of FPGA 100 are configured using various switches to generate signal paths for passing input and output signals between the CLBs and IOBs. These various switches include segment-to-segment switches, segment-to-CLB/IOB input switches, and CLB/IOB-to-segment output switches. Segment-to-segment switches include configurable circuitry that selectively connects wiring segments to form signal paths. Segment-to-CLB/IOB input switches include configurable circuitry that selectively connects the input wire 110 of a CLB (or IOB) to the end of a signal path. CLB/IOB-to-segment output switches include configurable circuitry that selectively connects the output wire 115 of a CLB (or IOB) to the beginning of a signal path.
FIG. 1(B) shows an example of a six-way segment-to-segment switch 122 that selectively connects vertical wiring segments 120(1) and 120(2), and horizontal wiring segments 121(1) and 121(2), in accordance with six-way switch configuration data stored in configuration memory cells M1 through M6. Six-way switch 122 includes normally-open pass transistors that are turned on to provide a signal path (or branch) between any two (or more) of the wiring segments in accordance with the six-way switch configuration data. For example, a signal path is provided between vertical wiring segment 120(1) and vertical wiring segment 120(2) by programming memory cell M5 to turn on its associated pass transistor. Similarly, a signal path is provided between vertical wiring segment 120(1) and horizontal wiring segment 121(2) by programming memory cell M1 to turn on its associated pass transistor. Similar signal paths between any two (or more) wiring segments are provided by selectively programming the relevant memory cell (or memory cells).
FIG. 1(C) shows an example of a segment-to-CLB/IOB input switch 123 that selectively connects an input wire 110(1) of a CLB (or IOB) to one or more interconnect wiring segments in accordance with input switch configuration data stored in configuration memory cells M7 and M8. Segment-to-CLB/IOB input switch 123 includes a multiplexer (MUX) having inputs connected to horizontal wiring segments 121(3) through 121(5) through buffers, and an output that is connected to CLB/IOB input wire 110(1). Memory devices M7 and M8 transmit control signals on select lines of the MUX such that the MUX passes a signal from one of the wiring segments 121(3) through 121(5) to the associated CLB (or IOB).
FIG. 1(D) shows an example of a CLB/IOB-to-segment output switch 124 that selectively connects an output wire 115(1) of a CLB (or IOB) to one or more interconnect wiring segments in accordance with input switch configuration data stored in configuration memory cells M9 through M11. CLB/IOB-to-segment output switch 124 includes three pass transistors connected between output wire 115(1) and horizontal wiring segments 120(3) through 120(5), and gates that are connected memory cells M9 through M11. Memory devices M9 through M11 store output switch configuration data that turns on selected pass transistors to pass output signals from the CLB (or IOB) to one or more of wiring segments 120(3) through 120(5).
As with most types of integrated circuits, PLD circuits are fabricated on silicon wafers using known silicon processing techniques. After the PLD circuits are formed, the wafers are diced into individual "chips", each chip including one PLD circuit. These chips are then packaged using known packaging technologies to form PLDs.
FIG. 2(A) is a simplified plan view showing a silicon wafer 200 that is fabricated to include multiple discrete circuits 210, each circuit 210 corresponding to one conventional FPGA 100 (see FIG. 1(A)). Each circuit 210 is separated from other circuits on wafer 200 by horizontal scribe lines 220 and vertical scribe lines 230. These scribe lines provide a predetermined distance between adjacent circuits 210 to prevent damage during the dicing process.
FIG. 2(B) is an enlarged view showing additional details regarding the fabrication of circuits 210 on wafer 200. In particular, FIG. 2(B) shows a portion of a row including circuits 210(1) and 210(2), each depicted with circuitry corresponding to the CLBs, IOBs and interconnect lines of FPGA 100 (see FIG. 1(A)). Circuit 210(1) is formed in an area defined by horizontal scribe lines 220(1) and 220(2), and vertical scribe lines 230(1) and 230(2). Similarly, circuit 210(2) is formed in an area defined by horizontal scribe lines 220(1) and 220(2), and vertical scribe lines 230(2) and 230(3). Note that circuit 210(1) is completely separated (electrically isolated) by vertical scribe line 230(2) from circuit 210(2). In particular, none of the interconnect lines of either circuit extends across vertical scribe line 230(2). Referring back to FIG. 2(A), all circuits 210 of wafer 200 are likewise separated by horizontal scribe lines 220 and vertical scribe lines 230.
FIG. 2(C) is a further enlarged view of wafer 200 showing further details associated with IOB circuits 240(1) and 240(2), which are respectively associated with circuit 210(1) and 210(2) (see FIG. 2(B)). Each IOB 240(1,2) is programmed to operate in either an input mode or an output mode by an output enable (OE) signal that is generated, for example, by configuration memory cells (not shown) of its associated circuit 210(1,2). The OE signal is transmitted to the first input of a two-input NAND gate 241, and through an inverter 242 to the first input of a two-input NOR gate 243. Each IOB 240(1) and 240(2) also receives data output (DATA OUT) signals from the CLBs of its associated circuit 210(1) and 240(2) via the interconnect lines (not shown). The DATA OUT signals are transmitted to the second inputs of NAND gate 241 and NOR gate 243. The output of NAND gate 241 is transmitted to the gate of a PMOS pull-up transistor 244 that is connected between Vcc and a bonding pad 246. The output of NOR gate 243 is transmitted to the gate of an NMOS pull-down transistor 245 that is connected between bonding pad 246 and ground. Bonding pad 246 is also connected through an input buffer 247 to a DATA IN line that transmits data input signals to the internal circuitry via the interconnect lines (not shown). After wafer 200 is diced into chips and the chips are mounted onto packages, bonding pads 246 of IOBs 240(1) and 240(2) are typically connected to, for example, pins of their respective package using wire bonding techniques. Note that, similar to the interconnect lines shown in FIG. 2(B), bonding pads 246 of IOBs 240(1) and 240(2) are separated by vertical scribe line 230(2).
FPGA manufacturers are constantly designing and manufacturing larger, faster FPGAs to keep pace with ever-increasing user demands. However, the largest currently available FPGA is restricted by a maximum reticle size of 22 mm by 22 mm, and is sometimes found to provide insufficient resources for some large user-defined logic operations.
A first method typically used to implement large user-defined logic operations is to connect together several individually packaged FPGAs on a printed circuit board (PCB). A problem with this method is that the connections must be made through the IOBs of the FPGAs and through conductors formed on the PCB, which limits the number of signal paths between the FPGAs and creates undesirable signal delays. Another problem is that the individually packaged FPGAs take up a large area of the PCB, thereby limiting miniaturization of the resulting product.
A second method that may be used to implement large user-defined logic operations is to combine two or more chips, each having a single FPGA circuit, in a multi-chip module (MCM) package. MCM packages provide a single base for supporting the two or more chips, and include conductors in the base that provide electrical connections between the FPGA circuits of the chips. However, contact between the chips and the conductors is prone to misalignment, thereby significantly decreasing system performance. Moreover, mounting the two or more chips onto the base requires an additional manufacturing step that increases manufacturing costs. Further, problems associated with limited signal paths and signal delays, similar to those associated with the first method (discussed above), are caused by signal transmission through the base.
A third method that may be used to implement large user-defined logic operations is to utilize an interconnection structure, commonly known as chip-on-board, in which bare chips are mounted on a board and interconnected by wire bonding techniques. Chip-on-board structures increase package density compared to conventional MCM packaging, thereby reducing system delays caused by transmission through the MCM package base. However, chip-on-board structures are expensive due to the physical operation of attaching wires between the individual bonding pads and the board. In addition, although reduced when compared to MCM packages, significant signal delays are still caused by signal transmission through the IOBs of the FPGA circuits, and through the wire bonds and conductors provided on the board. In addition, the same problem associated with limited signal paths discussed above also applied to the third method.
What is needed is a PLD layout architecture for fabricating a wafer that can be selectively diced into both single-device chips and multi-device chips.